There is a piece of advice that almost every electronics engineer learns very early:
“Put a 100 nF capacitor next to every IC!”
It is good advice. I do it myself.
The problem is when it becomes a rule that we apply without thinking about what the capacitor is actually there to do.
From working on electronics development, testing hardware and dealing with EMC problems, I have learned that a board can have plenty of decoupling capacitors and still suffer from noisy power rails, unstable analogue measurements, unexplained resets or EMC issues.
You open the schematic and everything looks correct:
100 nF here…
100 nF there…
Another 100 nF beside the microcontroller…
So why is the board still misbehaving?
Because decoupling is not really about putting a particular capacitor value next to an IC. It is about providing current where it is needed and keeping the impedance of the power distribution network low over the frequencies that matter.
And that is a much more interesting problem.
What Is the Decoupling Capacitor Actually Doing?
An IC does not normally consume current at a perfectly constant rate.
A microcontroller, FPGA, logic device or communication interface can demand very short bursts of current as internal transistors switch.
The regulator may be only a few centimetres away on the PCB, but at high frequency those few centimetres matter.
Tracks, vias and planes all have parasitic inductance. The regulator also has a finite response time.
So when the IC suddenly demands current, the regulator cannot necessarily provide it instantaneously.
The local decoupling capacitor helps supply that transient current.
Ideally, the high-frequency current loop is very small:
capacitor → IC supply pin → IC ground → capacitor
That is why I tend to think about the current path rather than simply asking:
“Is there a 100 nF capacitor next to this pin?”
Where is the current actually flowing?
How does it return?
How much loop area have I created?
Those questions tell you much more about whether the decoupling will actually work.
The PCB Layout Is Part of the Capacitor
This is something that becomes very obvious when you start looking at real PCBs rather than just schematics.
On the schematic, a capacitor is connected directly between VCC and GND.
Perfect.
On the PCB, perhaps the capacitor is 15 mm away, connected through a narrow track, then through a via to the power plane, while the ground connection takes another route back through the board.
Electrically, that is no longer the simple capacitor shown on the schematic.
The traces and vias are part of the circuit as well.
At high frequencies, their inductance can become significant enough that the capacitor is much less effective than expected.
I have seen plenty of designs where the capacitor was technically “close to the IC”, but the actual current loop told a very different story.
Sometimes moving a capacitor a few millimetres and improving its connection to the power and ground planes can be more effective than simply increasing its capacitance.
That is why placement matters.
A lot.
A 100 nF Capacitor Is Not 100 nF at Every Frequency
Another important point is that a real capacitor is not an ideal capacitor.
It has:
- capacitance;
- equivalent series resistance, or ESR;
- equivalent series inductance, or ESL.
At relatively low frequencies, its impedance behaves more or less as we expect:
As frequency increases, the capacitive impedance falls.
But eventually the parasitic inductance starts to dominate.
At the capacitor’s self-resonant frequency, the capacitive and inductive effects approximately cancel.
Above that frequency, the capacitor increasingly behaves like an inductor.
This is one of the reasons why saying:
“There is a 100 nF capacitor there.”
doesn’t really tell me enough.
I also want to know:
What package is it?
How is it connected?
What frequency range are we interested in?
What other capacitance is present on that rail?
And what does the impedance of the complete network look like?
Different Capacitors for Different Frequency Ranges
This is where using different capacitor values can make sense.
Noise on a power rail is rarely present at one single frequency.
You might have relatively slow load transients, switching regulator noise, clock harmonics and very fast digital edges all present on the same supply.
One capacitor value may not be the best solution across that complete frequency range.
A common approach is therefore to use capacitance values separated approximately by decades, for example:
10 µF → 1 µF → 100 nF → 10 nF
The general idea is that the larger capacitors help at lower frequencies, while progressively smaller capacitors can remain effective at higher frequencies.
So, in a simplified way, each capacitor is helping to cover a different part of the frequency spectrum.
This is something I have found particularly useful when thinking about noisy power rails and EMC. Instead of asking only how much capacitance is on the rail, it is often more useful to ask:
At which frequencies am I trying to keep the impedance low?
That changes the way you look at the problem.
However, there is an important catch.
Real capacitors do not neatly divide the spectrum into separate frequency bands.
A 10 µF capacitor does not suddenly stop working where the 1 µF capacitor takes over, and then the 100 nF takes over after that.
Their impedance curves overlap, and their parasitics interact.
So using capacitors by decades is a useful technique, but it should not become another blind design rule.
More Capacitors Can Actually Make Things Worse
This sounds counter-intuitive at first.
If one capacitor is good, surely four capacitors must be better?
Not necessarily.
When several capacitors of different values are connected in parallel, their capacitance, ESR and parasitic inductance interact.
This can produce resonances and anti-resonances in the power distribution network.
At an anti-resonant frequency, the impedance can actually become higher than it would have been with either capacitor individually.
So something like:
10 µF + 1 µF + 100 nF + 10 nF
may look like an excellent decoupling network on a schematic, but the real impedance curve can contain peaks that are not obvious at all from looking at the component values.
Modern ceramic capacitors make this particularly interesting because their ESR can be very low, which can make some of these resonances quite sharp.
For a straightforward embedded controller, I am not suggesting that every design requires a full PDN simulation.
But it is worth knowing that more capacitance does not automatically mean better decoupling.
If I am troubleshooting a specific noise problem, I would much rather understand the frequency involved before simply adding another capacitor.
Bulk Capacitance and Decoupling Are Not the Same Thing
I also tend to separate local high-frequency decoupling from bulk energy storage.
They are related, but they are doing different jobs.
A 100 nF capacitor close to a microcontroller supply pin may be ideal for very fast transient currents.
It is not necessarily going to support a larger load step caused by something such as:
- a radio module starting transmission;
- a relay energising;
- a display backlight switching;
- a motor starting;
- a processor suddenly entering a high-current operating mode.
Those events may need significantly more local energy storage.
That could mean 1 µF, 10 µF, 47 µF or more depending on the system.
I normally think about the supply network in layers:
local high-frequency decoupling → local bulk capacitance → main rail capacitance → regulator
Each part deals with a different aspect of the load.
Trying to make one 100 nF capacitor solve all of that is asking a lot from a very small component.
The Regulator Is Part of the Story
Sometimes we see noise on a rail and immediately start changing capacitors.
But the regulator itself matters.
Every regulator has a control loop and finite transient response.
Some regulators also have quite specific requirements for output capacitance and ESR.
So blindly adding more capacitance can occasionally create other problems.
When I see a noisy power rail, I prefer to ask:
- Is the regulator stable?
- Is the output capacitor within the manufacturer’s recommended range?
- What happens during a load transient?
- How is the regulator laid out?
- Where is its feedback being sensed?
- Is the noise coming from the regulator, or is another circuit injecting it onto the rail?
Simply adding another capacitor may make the waveform look better.
But I still want to know why it worked.
If I understand that, I know whether I have fixed the problem or just hidden it.
Ceramic Capacitors Can Be Surprisingly Deceptive
Another thing that is easy to forget is that the number written on the BOM may not be the capacitance you actually have in operation.
This is particularly relevant with high-value MLCCs.
A ceramic capacitor marked as 10 µF can lose a significant amount of its effective capacitance when DC bias is applied.
The exact behaviour depends on dielectric type, package, voltage rating and manufacturer.
So you may design assuming that you have 10 µF on a rail and discover that, at the actual operating voltage, the effective capacitance is considerably lower.
For critical rails, I like to check the manufacturer’s DC-bias curves rather than relying only on the nominal value.
It is one of those small details that can explain why a design behaves differently from what the schematic suggests it should.
Package Size Matters Too
Two capacitors with the same value can behave differently at high frequency simply because they use different packages.
A smaller package generally has lower parasitic inductance.
That means a 100 nF capacitor in 0402 may remain useful further into the high-frequency range than the same nominal capacitance in a much larger package.
Of course, smaller is not automatically better for everything.
There are manufacturing, rework, voltage and capacitance-density considerations.
But when I am looking at high-frequency decoupling, package size is definitely part of the decision.
Again, the component value is only one part of the story.
Decoupling and EMC Are More Closely Related Than They First Appear
My experience with EMC testing changed the way I look at decoupling.
It is very easy to think of decoupling purely as a power-supply issue.
But high-frequency current has to flow somewhere.
If we do not provide a short, low-impedance local path, that current will find another path.
Maybe through the ground plane.
Maybe through another circuit.
Maybe through a connector.
And sometimes through a cable that then becomes a surprisingly effective antenna.
At that point, what started as a power-integrity problem can become an EMC problem.
This is why, during PCB reviews, I pay particular attention to the relationship between:
- the IC;
- the decoupling capacitor;
- the power plane;
- the ground plane;
- and the vias connecting them.
A capacitor may look perfectly positioned visually, but the current path can still be poor.
EMC has taught me to follow the current.
It usually tells you much more than simply following the schematic.
Measure Before You Modify
When a prototype has a noisy supply rail, one of the first things we naturally do is put an oscilloscope probe on it.
But even that can lead us in the wrong direction.
A standard oscilloscope probe with a long ground lead creates a surprisingly large loop.
At high frequencies, that loop can pick up noise and produce ringing that is partly — or sometimes mostly — coming from the measurement setup.
I have learned to be cautious before reacting to every spike I see on an oscilloscope.
For power-integrity measurements, I much prefer using a short ground spring or another low-inductance probing method.
Otherwise, you can easily end up trying to fix noise that the PCB is not actually producing.
And that can lead to the familiar engineering process of changing three capacitors, adding a ferrite bead, redesigning half the board…
…only to discover that the original measurement was misleading.
How I Approach Decoupling in Practice
I still start with the datasheet.
If a manufacturer recommends a 100 nF capacitor directly beside every supply pin, I will normally follow that recommendation.
They know what is happening inside their device better than I do.
But I treat that as the starting point, not the complete power-integrity design.
From there, I look at the system.
What type of IC is it?
How fast are the edges?
What current transients should I expect?
What other loads share the rail?
Is the circuit analogue, digital or mixed-signal?
Where is the regulator?
What does the PCB stack-up look like?
Where will the current return?
Do I need capacitance covering several frequency decades?
Is there enough bulk capacitance locally?
Are there any particularly sensitive analogue references or ADC rails?
Are external cables going to provide an unwanted path for high-frequency current?
Those questions tend to give me much more confidence in a design than simply counting the number of 100 nF capacitors on the schematic.
So, Should We Stop Using 100 nF Capacitors?
Definitely not.
100 nF is still a very useful decoupling value, and it is entirely appropriate in a huge number of designs.
The point is simply that:
“Put 100 nF next to every IC” is a good starting rule, but it is not a power-integrity strategy.
Sometimes one 100 nF capacitor is exactly what you need.
Sometimes you need additional bulk capacitance.
Sometimes you need several capacitor values to keep the rail impedance low over a wider frequency range.
Sometimes changing from one package size to another helps.
Sometimes the problem is actually the placement or the vias.
Sometimes the regulator is the issue.
And sometimes the capacitor is perfectly fine and the noise is coming from somewhere completely different.
That is one of the things I enjoy about electronics engineering.
A component that costs pennies and occupies a few square millimetres of PCB can have a significant effect on whether a product is stable, quiet and EMC-compliant.
The schematic tells you that the capacitor is there.
The interesting engineering starts when you ask what it is actually doing in the real circuit.